This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-100148, Mar. 30, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly, to an electrically erasable and programmable semiconductor memory.
2. Description of the Related Art
As an electrically erasable and programmable nonvolatile semiconductor memory, a device having a MISFET structure in which a charge storage layer and a control gate electrode are stacked on a semiconductor substrate is known. Examples of devices of this type are a floating gate type nonvolatile semiconductor memory and a MONOS type nonvolatile semiconductor memory. MONOS represents xe2x80x9cMetal-Oxide-Nitride-Oxide-Semiconductorxe2x80x9d, and typically represents xe2x80x9cmetal-silicon oxide film-silicon nitride film-silicon oxide film-semiconductorxe2x80x9d.
FIGS. 25A to 25C are schematic views showing an erase operation in a memory cell of a conventional floating gate type nonvolatile semiconductor memory. As shown in FIGS. 25A to 25C, source/drain diffusion layers 102 are formed in the surface of a semiconductor substrate 101. On this semiconductor substrate 101, a floating gate layer 106 is formed via a tunnel insulating film 103. On this floating gate layer 106, a control gate electrode 104 is formed via an inter-poly-Si insulating film 105.
FIG. 25A shows a state in which the floating gate layer 106 is negatively charged. In this state, as shown in FIG. 25B, this negative charge is extracted from the floating gate layer 106 to the semiconductor substrate 101. Consequently, as shown in FIG. 25C, the floating gate layer 106 is positively charged to perform an erasing action.
FIGS. 26A to 26C are schematic views showing an erase operation in a memory cell of a conventional MONOS type nonvolatile semiconductor memory. As shown in FIGS. 26A to 26C, source/drain diffusion layers 102 are formed in the surface of a semiconductor substrate 101. On this semiconductor substrate 101, a charge storage layer 110 is formed via a tunnel insulating film 111. On this charge storage layer 110, a control gate electrode 104 is formed via a block insulating film 105.
FIG. 26A shows a state in which the charge storage layer 110 is negatively charged. In this state, as shown in FIG. 26B, positive charge is injected into the charge storage layer 110 from the semiconductor substrate 101. Consequently, as shown in FIG. 26C, the charge storage layer is positively charged to perform an erasing action. This operation is called direct tunneling of positive charge. In this operation, as the thickness of the tunnel insulating film 111 increases, it becomes more difficult for positive charge to enter the charge storage layer. However, the tunnel insulating film is preferably thick for the sake of the data retention characteristic.
FIG. 27A is a graph showing threshold voltage distributions in data storage states (an erased state D1 and a written state D2) in a conventional nonvolatile semiconductor memory. FIGS. 27B and 27C are schematic views showing the written state and erased state, respectively, which correspond to the distributions in FIG. 27A, of a memory cell.
A nonvolatile semiconductor memory usually changes the threshold voltage of a memory cell transistor by a charge amount stored in a charge storage layer, thereby storing a written state and erased state. A state in which the charge amount in the charge storage layer is 0 is called a neutral state, and the threshold voltage of the memory cell transistor in this state is a neutral threshold voltage Vthi. A state in which positive charge is stored in the charge storage layer is an erased state, and a state in which negative charge is stored is a written state. These states are common to NAND, AND, and NOR memories.
Referring to FIG. 27A, the abscissa indicates the number of memory cells, and the ordinate indicates the threshold voltage. In the erased state D1, all the threshold voltages of the memory cells are distributed at values smaller than Vthi. In the written state D2, all the threshold voltages of the memory cells are distributed at values larger than Vthi. As shown in FIG. 27B, data write is performed by, e.g., applying a high voltage (e.g., 10 to 25 V) to a control gate electrode 104 with a semiconductor substrate 101 set at 0 V, thereby injecting negative charge into a charge storage layer 110 from the semiconductor substrate 101. Alternatively, data is written by biasing the drain potential positively with respect to the source potential to generate hot electrons accelerated by the channel, and biasing the control gate electrode 104 positively with respect to the source potential to inject these hot electrons into the charge storage layer.
As shown in FIG. 27C, data is erased by, e.g., applying a high voltage (e.g., 8 to 25 V) to the semiconductor substrate 101, with the control gate electrode 104 set at 0 V, thereby releasing negative charge from the charge storage layer 110 to the semiconductor substrate 101, or thereby injecting positive charge into the charge storage layer 110 from the semiconductor substrate 101. Alternatively, data is erased by biasing the source or drain, or the source/drains positively with respect to the well, and biasing the control gate electrode negatively with respect to the well, to inject hot holes into the charge storage layer 110.
FIG. 28 is a graph showing threshold voltage distributions in data storage states (an erased state D1 and a written state D2) in a conventional NAND memory cell. FIG. 29 is a circuit diagram for explaining a read operation in this conventional NAND memory cell. The data storage states and read operation in a NAND EEPROM as a representative nonvolatile semiconductor memory will be explained with reference to FIGS. 28 and 29.
In a general NAND EEPROM, a state in which the threshold voltage of a memory cell is higher than 0 V is a written state, and a state in which the threshold voltage of a memory cell is lower than 0 V is an erased state. Referring to FIG. 28, the abscissa indicates the number of memory cells, and the ordinate indicates the threshold voltage. In the erased state D1 (the state shown in FIG. 27C), all the threshold voltages of the memory cells are distributed at values smaller than Vthi and a threshold voltage Vthsg of a selection transistor. In the written state D2 (the state shown in FIG. 27B), all the threshold voltages of the memory cells are distributed at values larger than Vthi and Vread.
As shown in FIG. 29, in a read operation of a NAND EEPROM, a bit line BL is set to float after being precharged, and a source line Source is set at 0 V. In this state, the voltage of the control gate electrode of a memory cell M2 selected for data read is set at a read voltage of 0 V, the voltages of the control gate electrodes of other memory cells M0, M1, and M3 to M31 are set at a non-selection read voltage Vread, and the gate voltages of selection transistors S1 and S2 are set at a power supply voltage Vcc. Data is read by detecting, by the bit line BL, whether an electric current flows through the memory cell M2 selected for data read.
In the written state in which the threshold voltage Vth of the memory cell M2 selected for data read is positive, this memory cell M2 is turned off, so the bit line BL maintains the precharge voltage. On the other hand, in the read state in which the threshold voltage Vth of the memory cell M2 selected for data read is negative, this memory cell M2 is turned on, so the potential of the bit line BL lowers from the precharge potential by xcex94V. Data in this memory cell M2 is read out by sensing this potential change by a sense amplifier.
According to an aspect of the present invention, there is provided a semiconductor memory comprising a plurality memory elements, which are connected between at least two current terminals, and each of which comprises:
at least one control terminal which switches a ON state and OFF state of a current path between the current terminals; and
an information storage portion interposed between the current path and the control terminal to provide a threshold voltage which is a voltage of the control terminal when the ON state and OFF state of the current path are switched,
wherein the information storage portion selectively stores electrically erasable and programmable discrete N-valued (N is an integer of not less than 2) data,
the information storage portion provides, as the threshold voltage, first to Nth threshold voltages which are discrete in ascending order of voltage in correspondence with the N-valued data,
all the first to Nth threshold voltages of the plurality of memory elements are higher than the lower one of voltages applied to the current terminals in data read, and
a voltage higher than the Nth threshold voltage is applied to at least one control terminal of the plurality of memory elements in data read.